|
| constexpr size_t | XFER_MAX_SIZE = I2C_BUFFER_LENGTH |
| | XFER_MAX_SIZE defines the maximum number of bytes allowed during one transfer.
|
| |
| constexpr size_t | FIFO_SIZE = 256 |
| | size of the internal WeiKai FIFO
|
| |
| constexpr size_t | RING_BUFFER_SIZE = FIFO_SIZE |
| | size of the ring buffer set to size of the FIFO
|
| |
| constexpr uint8_t | WKREG_GENA = 0x00 |
| | Global Control Register - 00 0000.
|
| |
| constexpr uint8_t | GENA_C4EN = 1 << 3 |
| | Channel 4 enable clock (0: disable, 1: enable)
|
| |
| constexpr uint8_t | GENA_C3EN = 1 << 2 |
| | Channel 3 enable clock (0: disable, 1: enable)
|
| |
| constexpr uint8_t | GENA_C2EN = 1 << 1 |
| | Channel 2 enable clock (0: disable, 1: enable)
|
| |
| constexpr uint8_t | GENA_C1EN = 1 << 0 |
| | Channel 1 enable clock (0: disable, 1: enable)
|
| |
| constexpr uint8_t | WKREG_GRST = 0x01 |
| | Global Reset Register - 00 0001.
|
| |
| constexpr uint8_t | GRST_C4RST = 1 << 3 |
| | Channel 4 soft reset (0: not reset, 1: reset)
|
| |
| constexpr uint8_t | GRST_C3RST = 1 << 2 |
| | Channel 3 soft reset (0: not reset, 1: reset)
|
| |
| constexpr uint8_t | GRST_C2RST = 1 << 1 |
| | Channel 2 soft reset (0: not reset, 1: reset)
|
| |
| constexpr uint8_t | GRST_C1RST = 1 << 0 |
| | Channel 1 soft reset (0: not reset, 1: reset)
|
| |
| constexpr uint8_t | WKREG_GMUT = 0x02 |
| | Global Master channel control register (not used) - 000010.
|
| |
| constexpr uint8_t | WKREG_GIER = 0x10 |
| | Global interrupt register (not used) - 01 0000.
|
| |
| constexpr uint8_t | WKREG_GIFR = 0x11 |
| | Global interrupt flag register (not used) 01 0001.
|
| |
| constexpr uint8_t | WKREG_GPDIR = 0x21 |
| | Global GPIO direction register - 10 0001.
|
| |
| constexpr uint8_t | WKREG_GPDAT = 0x31 |
| | Global GPIO data register - 11 0001.
|
| |
| constexpr uint8_t | WKREG_SPAGE = 0x03 |
| | Global Page register c0/c1 0011.
|
| |
| constexpr uint8_t | WKREG_SCR = 0x04 |
| | Serial Control Register - c0/c1 0100.
|
| |
| constexpr uint8_t | SCR_TXEN = 1 << 1 |
| | transmission control (0: enable, 1: disable)
|
| |
| constexpr uint8_t | SCR_RXEN = 1 << 0 |
| | receiving control (0: enable, 1: disable)
|
| |
| constexpr uint8_t | WKREG_LCR = 0x05 |
| | Line Configuration Register - c0/c1 0101.
|
| |
| constexpr uint8_t | LCR_PAEN = 1 << 3 |
| | Parity enable (0: no check, 1: check)
|
| |
| constexpr uint8_t | LCR_PAR_F0 = 0 << 1 |
| | Parity force 0.
|
| |
| constexpr uint8_t | LCR_PAR_ODD = 1 << 1 |
| | Parity odd.
|
| |
| constexpr uint8_t | LCR_PAR_EVEN = 2 << 1 |
| | Parity even.
|
| |
| constexpr uint8_t | LCR_PAR_F1 = 3 << 1 |
| | Parity force 1.
|
| |
| constexpr uint8_t | LCR_STPL = 1 << 0 |
| | Stop length (0: 1 bit, 1: 2 bits)
|
| |
| constexpr uint8_t | WKREG_FCR = 0x06 |
| | FIFO Control Register - c0/c1 0110.
|
| |
| constexpr uint8_t | FCR_TFEN = 1 << 3 |
| | Transmitter FIFO enable.
|
| |
| constexpr uint8_t | FCR_RFEN = 1 << 2 |
| | Receiver FIFO enable.
|
| |
| constexpr uint8_t | FCR_TFRST = 1 << 1 |
| | Transmitter FIFO reset.
|
| |
| constexpr uint8_t | FCR_RFRST = 1 << 0 |
| | Receiver FIFO reset.
|
| |
| constexpr uint8_t | WKREG_SIER = 0x07 |
| | Serial Interrupt Enable Register (not used) - c0/c1 0111.
|
| |
| constexpr uint8_t | WKREG_SIFR = 0x08 |
| | Serial Interrupt Flag Register (not used) - c0/c1 1000.
|
| |
| constexpr uint8_t | WKREG_TFCNT = 0x09 |
| | Transmitter FIFO Count - c0/c1 1001.
|
| |
| constexpr uint8_t | WKREG_RFCNT = 0x0A |
| | Receiver FIFO count - c0/c1 1010.
|
| |
| constexpr uint8_t | WKREG_FSR = 0x0B |
| | FIFO Status Register - c0/c1 1011.
|
| |
| constexpr uint8_t | FSR_RFOE = 1 << 7 |
| | Receiver FIFO Overflow Error (0: no OE, 1: OE)
|
| |
| constexpr uint8_t | FSR_RFLB = 1 << 6 |
| | Receiver FIFO Line Break (0: no LB, 1: LB)
|
| |
| constexpr uint8_t | FSR_RFFE = 1 << 5 |
| | Receiver FIFO Frame Error (0: no FE, 1: FE)
|
| |
| constexpr uint8_t | FSR_RFPE = 1 << 4 |
| | Receiver Parity Error (0: no PE, 1: PE)
|
| |
| constexpr uint8_t | FSR_RFDAT = 1 << 3 |
| | Receiver FIFO count (0: empty, 1: not empty)
|
| |
| constexpr uint8_t | FSR_TFDAT = 1 << 2 |
| | Transmitter FIFO count (0: empty, 1: not empty)
|
| |
| constexpr uint8_t | FSR_TFFULL = 1 << 1 |
| | Transmitter FIFO full (0: not full, 1: full)
|
| |
| constexpr uint8_t | FSR_TBUSY = 1 << 0 |
| | Transmitter busy (0 nothing to transmit, 1: transmitter busy sending)
|
| |
| constexpr uint8_t | WKREG_LSR = 0x0C |
| | Line Status Register (not used - using FIFO)
|
| |
| constexpr uint8_t | WKREG_FDAT = 0x0D |
| | FIFO Data Register (not used - does not seems to work)
|
| |
| constexpr uint8_t | WKREG_BRH = 0x04 |
| | Baud rate configuration register: high byte - c0/c1 0100.
|
| |
| constexpr uint8_t | WKREG_BRL = 0x05 |
| | Baud rate configuration register: low byte - c0/c1 0101.
|
| |
| constexpr uint8_t | WKREG_BRD = 0x06 |
| | Baud rate configuration register decimal part - c0/c1 0110.
|
| |
| constexpr uint8_t | WKREG_RFI = 0x07 |
| | Receive FIFO Interrupt trigger configuration (not used) - c0/c1 0111.
|
| |
| constexpr uint8_t | WKREG_TFI = 0x08 |
| | Transmit FIFO interrupt trigger configuration (not used) - c0/c1 1000.
|
| |
When the TEST_COMPONENT flag is defined we include some auto-test methods.
Used to test the software during development but can also be used in situ to test if the component is working correctly. For release we do not set it by default but you can set it by using the following lines in you configuration file:
platformio_options:
build_flags:
- -DTEST_COMPONENT